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AMD - Adaptable Learning

AMD Offerings

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Design Process

	AI Engine Development
	Board System Design
	Embedded Software Development
	Hardware IP & Platform Development
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	Machine Learning and Data Science
	System and Solution Planning
	System Integration and Validation

Silicon

	7 series
	Alveo
	Kria
	MPSoC
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	RFSoC
	UltraScale/UltraScale+
	Versal
	Zynq

Tools

	DNNDK
	Dynamic Function eXchange
	HLS
	IP Integrator
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	ISE
	ML Suite
	Model Composer
	Partial Reconfiguration
	PetaLinux
	SDAccel
	SDSoC
	SysGen
	UFDM
	Vitis
	Vitis AI
	Vitis IDE
	Vivado
	Xilinx SDK

Technology

	AWS
	DSP
	Embedded
	Functional Safety & Security
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	Machine Learning
	PCB
	PCIE
	Power & Thermal
	SLD

Delivery Type

	OnDemand
	Live Classroom
	Virtual Classroom

Language

English

Market

	A&D
	Auto
	AVB
	Competitive
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	Data Center
	ISM
	TME
	Wired & Wireless

Free Course

OnDemand

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Adaptive SoCs for System Architects

This course provides system architects with an overview of the capabilities and support for the AMD Zynq™ UltraScale+™ MPSoC and Versal™ adaptive SoC devices.The emphasis is on:Utilizing power management strategies ef...

Design Closure Techniques

Learn how to achieve design closure more efficiently and productively by using the three pillars of design closure (functional closure, timing closure, and power closure). Also learn how to solve functional behavior, ...

Designing FPGAs Using the Vivado Design Suite 1

This course offers introductory training on the AMD Vivado™ Design Suite and demonstrates the FPGA design flow for those uninitiated to FPGA design.The course provides experience with:Creating a Vivado Design Suite pr...

Designing FPGAs Using the Vivado Design Suite 2

Learn how to build a more effective FPGA design:The focus is on:Using synchronous design techniquesUtilizing the Vivado™ IP integrator to create a sub-systemPerforming power analysis and optimization to improve the po...

Designing FPGAs Using the Vivado Design Suite 3

Learn how to effectively employ timing closure techniques. This course includes: Demonstrating timing closure techniques such as baselining, pipelining, and synchronization circuits Showing optimum HDL cod...

Designing FPGAs Using the Vivado Design Suite 3 - Virtual Board

Learn how to effectively employ timing closure techniques.This course includes:Demonstrating timing closure techniques such as baselining, pipelining, and synchronization circuitsShowing optimum HDL coding techniques ...

Designing FPGAs Using the Vivado Design Suite 4

Learn how to use the advanced aspects of the Vivado™ Design Suite.The focus is on:Applying techniques to reduce delay and to improve clock skew and clock uncertaintyUtilizing floorplanning techniquesEmploying advanced...

Designing with the IP Integrator Tool

Explore the Vivado™ IP integrator tool and its features to gain the expertise needed to develop, implement, and debug different IP integrator block designs using the Vivado Design Suite.This course focuses on:Creating...

Designing with the Spartan UltraScale+ FPGA: Architecture

Learn about the key features and architecture of the AMD Spartan™ UltraScale+™ FPGA, including its advanced I/O, high-speed transceivers, substantial built-in and external memory, PCIe® Gen4 connectivity, and modern s...

Designing with the UltraScale and UltraScale+ Architectures

This course introduces the UltraScale™ and UltraScale+™ architectures to both new and experienced designers.The emphasis is on:Introducing CLB resources, clock management resources (MMCM and PLL), global and regional ...

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