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uvm

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Here are 349 public repositories matching this topic...

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cocotb / cocotb

Star 2.4k

cocotb: Python-based chip (RTL) verification

python test vhdl verification verilog uvm
  • Updated Jul 7, 2026
  • Python

openhwgroup / core-v-verif

Star 694

Functional verification project for the CORE-V family of RISC-V cores.

verification systemverilog uvm risc-v
  • Updated Jun 22, 2026
  • Assembly

maximecb / uvm

Sponsor
Star 591

Fun, portable, minimalistic virtual machine.

emulator rust interpreter bytecode compiler virtual-machine emulation sandboxing jit-compiler uvm containerization bytecode-interpreter permacomputing
  • Updated Jul 7, 2026
  • Rust

taichi-ishitani / tvip-axi

Sponsor
Star 469

AMBA AXI VIP

vip systemverilog uvm axi amba axi4 amba-axi
  • Updated Jun 28, 2024
  • SystemVerilog

chipsalliance / Surelog

Star 465

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

parser linter preprocessor antlr verilog python-api systemverilog uvm elaboration vpi antlr4-grammar parser-ast vpi-api vpi-standard
  • Updated Jul 1, 2026
  • C++

rggen / rggen

Star 461

Code generation tool for control and status registers

asic fpga vhdl eda rtl verilog csr systemverilog soc uvm ral axi amba apb register-descriptions wishbone-bus uvm-ral-model uvm-register-model wiki-documents
  • Updated Jul 2, 2026
  • Ruby

troyguo / awesome-dv

Star 363

Awesome ASIC design verification

asic verification uvm formal-verification asic-verification
  • Updated Feb 9, 2022

tymonx / logic

Star 290

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

cmake asic fpga cpp verification rtl verilog xilinx vivado systemverilog systemc unit-tests hdl modelsim uvm verilator quartus testing-rtl
  • Updated Nov 25, 2019
  • SystemVerilog

Nic30 / hwt

Star 225

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

simulator fpga compiler hls vhdl rtl verilog hcl codegenerator codegen systemverilog systemc uvm
  • Updated Jun 22, 2026
  • Python

taichi-ishitani / tnoc

Sponsor
Star 210

Network on Chip Implementation written in SytemVerilog

systemverilog uvm noc axi amba network-on-chip axi4 amba-axi
  • Updated Aug 27, 2022
  • SystemVerilog

Juniper / open-register-design-tool

Star 208

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

asic fpga eda systemverilog uvm registers systemrdl jspec register-descriptions systemrdl-compiler
  • Updated Jun 3, 2026
  • Verilog

SystemRDL / PeakRDL

Star 198

Control and status register code generator toolchain

asic fpga eda verilog csr command-line-tool systemverilog uvm registers axi amba apb register-descriptions systemrdl-compiler hardware-description-language uvm-register-model
  • Updated May 5, 2026
  • Python

kumarrishav14 / AXI

Star 179

VIP for AXI Protocol

uvm sv asic-verification amba-axi design-verification
  • Updated May 24, 2022
  • SystemVerilog

erihsu / INT_FP_MAC

Star 124

INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.

verilog systemverilog uvm accumulator
  • Updated Apr 3, 2026
  • Verilog

gupta409 / Processor-UVM-Verification

Star 123

System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment

processor verilog systemverilog uvm verilog-hdl systemverilog-simulation
  • Updated Dec 29, 2024
  • Verilog

nelsoncsc / ISP_UVM

Star 120

A Framework for Design and Verification of Image Processing Applications using UVM

opencv image-processing hardware-designs systemc uvm systemverilog-hdl functional-verification
  • Updated Nov 27, 2017
  • SystemVerilog

Siddhi-95 / AHB-to-APB-Bridge-Verification

Star 115

Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.

verilog systemverilog uvm
  • Updated Jul 2, 2023
  • SystemVerilog

Shehab-Naga / ddr5_phy

Star 86

DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision

systemverilog uvm gp
  • Updated Mar 21, 2024
  • SystemVerilog

zhajio1988 / YASA

Star 81

🐌Yet Another Simulation Architecture

uvm sv ic dv
  • Updated Sep 17, 2020
  • Python

dadongshangu / async_FIFO

Star 67

This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is coded by me(Xianghzi Meng)

asynchronous fifo uvm verification-code async-fifo verilog-tb
  • Updated Oct 19, 2023
  • SystemVerilog
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