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#

timing-analysis

Here are 57 public repositories matching this topic...

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

  • Updated Jul 8, 2026
  • Verilog

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

  • Updated Jul 7, 2026
  • Verilog

AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BRAM...)

  • Updated Mar 9, 2024
  • C++

Easily benchmark PyTorch model FLOPs, latency, throughput, allocated gpu memory and energy consumption

  • Updated Aug 25, 2023
  • Python

This is a tutorial on standard digital design flow

  • Updated May 24, 2021
  • Tcl

This repository contains code and data for "Tik-Tok: The Utility of Packet Timing in Website Fingerprinting Attacks" paper, published in PETS 2020.

  • Updated Jun 16, 2026
  • Python

Gate-level timing estimation toolkit

  • Updated Apr 11, 2022
  • Shell

A NuGet that allows you to use a Azure DevOps Service Hook to track workitems changes in a simply and detailed way.

  • Updated Aug 18, 2025
  • C#

Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format

  • Updated Feb 13, 2020
  • C++

Evaluation Framework for Self-Suspending Task Systems

  • Updated Feb 24, 2026
  • Python

GG for Arduino is a serial console library. It also contains various functions for implementing the console, for example printf(). You can implement a command line interface on your Arduino and add your own commands. This library contains built-in commands that allow memory access and timing analysis.

  • Updated Nov 26, 2023
  • C

Compiler backend from packing to bitstream generation.

  • Updated Dec 3, 2024
  • C++

Detect side channels with statistically rigorous methods.

  • Updated Apr 22, 2026
  • Rust

Static Timing Analyser (LIP6)

  • Updated Dec 30, 2025
  • C

Engineering notes and reproducible FPGA examples from real-world development, including RTL design, simulation, verification and debugging.

  • Updated Jun 26, 2026
  • Verilog

SerDes RTL design, verification using UVM and Physical design.

  • Updated May 26, 2024
  • Verilog

Academic-grade Worst-Case Execution Time analysis using LLVM infrastructure for embedded systems and real-time applications

  • Updated Nov 4, 2025
  • TypeScript

ttcp is a simple Rust-coded tool to measure TCP timing and detect anomalies.

  • Updated Oct 17, 2025
  • Rust

RTAS 2021 - Artifact Evaluation for "Timing Analysis of Asynchronized Distributed Cause-Effect Chains"

  • Updated Mar 26, 2021
  • Python

Analysis of radio pulsar parameters and their relationships with nulling statistics

  • Updated Feb 20, 2022
  • Jupyter Notebook
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