AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Parametric AXI4 crossbar in SystemVerilog

AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

AXI4 and AXI4-Lite interface definitions

Basic USB 1.1 Host Controller for small FPGAs

Audio controller (I2S, SPDIF, DAC)

USB -> AXI Debug Bridge

HLS for Networks-on-Chip

Interface definitions for VHDL-2019.

Master and Slave made using AMBA AXI4 Lite protocol.

This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.

SystemVerilog AXI verification library and video-DMA IP: AXI4/Lite/Stream BFMs, triple-buffer VDMA, and multi-tap temporal VDMA with byte-exact real-image round-trip tests. Verilator · Yosys · Docker · CI.

Formal AXI verification properties from the eXpect framework for secure SoC validation

Multi-port BRAM IP for ASIC and FPGA

Axion-HDL: Automated AXI Register Space Generation Tool

VHDL generator from SystemRDL

A tutorial on the usage of AXI4-Lite and AXI4-Stream Interfaces on HW Accelerators generated through High-Level Synthesis (HLS)

A UVM-based verification environment for a multi-core, write-back L2 cache on 32-bit RISC-V, enforcing MESI coherence with L1 caches and interfacing to DRAM over AXI4-Lite.

A collection of formal properties for hardware buses, and cores using them.

This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .